IC培训
   
 
 
   班级规模及环境
       为了保证培训效果,增加互动环节,我们坚持小班授课,每期报名人数限3到5人,多余人员安排到下一期进行。
   上课时间和地点
上课地点:【上海】同济大学(沪西)/新城金郡商务楼(11号线白银路站) 【深圳分部】:电影大厦(地铁一号线大剧院站)/深圳大学成教院 【北京分部】:北京中山学院/福鑫大楼 【南京分部】:金港大厦(和燕路) 【武汉分部】:佳源大厦(高新二路) 【成都分部】:领馆区1号(中和大道) 【沈阳分部】:沈阳理工大学/六宅臻品 【郑州分部】:郑州大学/锦华大厦 【石家庄分部】:河北科技大学/瑞景大厦
最近开课时间(周末班/连续班/晚班):2018年11月19日
   学时
     ◆课时: 共5天,30学时
        ◆外地学员:代理安排食宿(需提前预定)
        ☆注重质量 ☆边讲边练

        ☆合格学员免费推荐工作
        ★实验设备请点击这儿查看★
   质量保障

        1、培训过程中,如有部分内容理解不透或消化不好,可免费在以后培训班中重听;
        2、培训结束后,培训老师留给学员手机和Email,免费提供半年的技术支持,充分保证培训后出效果;
        3、培训合格学员可享受免费推荐就业机会。 ☆合格学员免费颁发相关工程师等资格证书,提升您的职业资质。专注高端培训13年,曙海提供的证书得到本行业的广泛认可,学员的能力得到大家的认同,受到用人单位的广泛赞誉。

课程大纲
 
  1. Synopsys SystemVerilog验证培训
    课程描述:
    第一阶段 SystemVerilog Assertions培训
  2. COURSE OUTLINE
    * Introduction to assertions
    * SVA checker library
    * Use Model and debug flow using DVE
    * Basic SVA constructs
    * Temporal behavior, Data Consistency
    * Coverage, Coding Guidelines
  3. 第二阶段 SystemVerilog Testbench
  4. Overview
  5. In this intensive, three-day course, you will learn the key features and benefits of the SystemVerilog testbench language and its use in VCS.
    This course is a hands-on workshop that reinforces the verification concepts taught in lecture through a series of labs. At the end of this class, students should have the skills required to write an object-oriented SystemVerilog testbench to verify a device under test with coverage-driven constrained-random stimulus using VCS.
    Students will first learn how to develop an interface between the SystemVerilog test program and the Device Under Test (DUT). Next the workshop will explain how the intuitive object-oriented technology in SystemVerilog testbench can simplify verification problems. Randomization of data is covered to show how different scenarios for testing may be created. This course concludes with an in-depth discussion of functional coverage including a uniform, measurable definition of functionality and the SystemVerilog constructs that allow you to assess the percentage of functionality covered, both dynamically and through the use of generated reports.
    To reinforce the lecture and accelerate mastery of the material, each student will complete a challenging test suite for real-world, system-based design.
    Objectives
    At the end of this workshop the student should be able to:
    Build a SystemVerilog verification environment
    Define testbench components using object-oriented programing.
    Develop a stimulus generator to create constrained random test stimulus
    Develop device driver routines to drive DUT input with stimulus from generator
    Develop device monitor routines to sample DUT output
    Develop self-check routines to verify correctness of DUT output
    Abstract DUT stimulus as data objects
    Execute device drivers, monitors and self-checking routines concurrently
    Communicate among concurrent routines using events, semaphores and mailboxes
    Develop functional coverage to measure completeness of test
    Use SystemVerilog Packages
    Course Outline
    Uunit 1
    The Device Under Test
    SystemVerilog Verification Environment
    SystemVerilog Testbench Language Basics
    Driving and Sampling DUT Signals
    Uunit 2
    Managing Concurrency in SystemVerilog
    Object Oriented Programming: Encapsulation
    Object Oriented Programming: Randomization
    Uunit 3
    Object Oriented Programming: Inheritance
    Inter-Thread Communications
    Functional Coverage
    SystemVerilog UVM preview
  6. 第三阶段 Synopsys SystemVerilog VMM培训
  7. SystemVerilog Verification Using VMM Methodology
    OVERVIEW
    In this hands-on workshop, you will learn how to develop a VMM SystemVerilog test environment structure which can implement a number of different test cases with minimal modification. Within this VMM environment structure, you will develop stimulus factories, check and coverage callbacks, message loggers, transactor managers, and data flow managers. Once the VMM environment has been created, you will learn how to easily add extensions for more test cases.
    After completing the course, you should have developed the skills to write a coverage-driven random stimulus based VMM testbench that is robust, re-useable and scaleable.
    OBJECTIVES
    At the end of the course you should be able to:
    Develop an VMM environment class in SystemVerilog
    Implement and manage message loggers for printing to terminal or file
    Build a random stimulus generation factory
    Build and manage stimulus transaction channels
    Build and manage stimulus transactors
    Implement checkers using VMM callback methods
    Implement functional coverage using VMM callback methods
    COURSE OUTLINE
    Unit 1
    SystemVerilog class inheritance review
    VMM Environment
    Message Service
    Data model
    Unit 2
    Stimulus Generator/Factory
    Check & Coverage
    Transactor Implementation
    Data Flow Control
    Scenario Generator
    Recommendations
  8. 第四阶段 SystemVerilog Verification using UVM
    Overview
    In this hands-on workshop, you will learn how to develop a UVM 1.1 SystemVerilog testbench environment which enables efficient testcase development. Within this UVM 1.1 environment, you will develop stimulus sequencer, driver, monitor, scoreboard and functional coverage. Once the UVM 1.1 environment has been created, you will learn how to easily manage and modify the environment for individual testcases.
    Objectives
    At the end of this workshop the student should be able to:
    Develop UVM 1.1 tests
    Implement and manage report messages for printing to terminal or file
    Create random stimulus and sequences
    Build and manage stimulus sequencers, drivers and monitors
    Create configurable agents containing sequencer, driver and monitor for re-use
    Create and manage configurable environments including agents, scoreboards, TLM ports and functional coverage objects
    Implement a collection of testcases each targeting a corner case of interest
    Create an abstraction of DUT registers and manage these registers during test, including functional coverage and self-test
    Audience Profile
    Design or Verification engineers who develop SystemVerilog testbenches using UVM 1.1 base classes.
    Prerequisites
    To benefit the most from the material presented in this workshop, students should have completed the SystemVerilog Testbench workshop.
    Course Outline
    Unit 1
    SystemVerilog OOP Inheritance Review
    Polymophism
    Singleton Class
    Singleton Object
    Proxy Class
    Factory Class
    UVM Overview
    Key Concepts in UVM: Agent, Environment and Tests
    Implement UVM Testbenches for Re-Use across Projects
    Code, Compile and Run UVM Tests
    Inner Workings of UVM Simulation including Phasing
    Implement and Manage User Report Messages
    Modeling Stimulus (Transactions)
    Transaction Property Implementation Guidelines
    Transaction Constraint Guidelines
    Transaction Method Automation Macros
    User Transactiom Method Customization
    Implement Tests to Control Transaction Constraints
    Creating Stimulus Sequences
    Sequence Execution Protocol
    Using UVM Macros to create and manage Stimulus
    Implementing User Sequences
    Implicitly Execute Sequences Through Configuration in Environment
    Explicitly Execute Sequences in Test
    Control Sequences through Configuration
    Unit 2
    Component Configuration and Factory
    Establish and Query Component Parent-Child Relationships
    Set Up Component Virtual SystemVerilog Interfaces with uvm_config_db
    Constructing Components and Transactions with UVM Factory
    Implement Tests to Configure Components
    Implement Tests to Override Components with Modified Behavior
    TLM Communications
    TLM Push, Pull and Fifo Modes
    TLM Analysis Ports
    TLM Pass-Through Ports
    TLM 2.0 Blocking and Non-Blocking Transport Sockets
    DVE Waveform Debugging with Recorded UVM Transactions
    Scoreboard & Coverage
    Implement scoreboard with UVM In-Order Class Comparator
    Implement scoreboard UVM Algorithmic Comparator
    Implement Out-Of-Order Scoreboard
    Implement Configuration/Stimulus/Correctness Coverage
    UVM Callback
    Create User Callback Hooks in Component Methods
    Implement Error Injection with User Defined Callbacks
    Implement Component Functional Coverage with User Defined Callbacks
    Review Default Callbacks in UVM Base Class
    Unit 3
    Virtual Sequence/Sequencer
    Disable Selected Sequencer in Agents through the Sequencer抯 揹efault? Configuration Field
    Implement Virtual Sequence and Sequencer to Manager Sequence Execution within Different Agents
    Implement uvm_event for Synchronization of Execution among Sequences in the Virtual Sequence
    Implement Grab and Ungrab in Sequences for exclusive access to Sequencer
    More on Phasing
    Managing Objections within Component Phases
    Implement Component Phase Drain Time
    Implement Component Phase Domain Synchronization
    Implement User Defined Domain and Phases
    Implement UVM Phase Jumping
    Register Layer Abstraction (RAL)
    DUT Register Configuration Testbench Architecture
    Develop DUT Register Abstration (.ralf) File
    Use ralgen Utility to Create UVM Register Model Class Files
    Create UVM Register Adapter Class
    Develop and Execute Sequences Using UVM Register Models
    Use UVM Built-In Register Tests to Verify DUT Register Operation
    Enable RAL Functional Coverage
    Summary
    Review UVM Methodology
    Review Run-Time Command Line Debug Switche

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曙海教育实验设备
android开发板
linux_android开发板
fpga图像处理
曙海培训实验设备
fpga培训班
 
本课程部分实验室实景
曙海实验室
实验室
曙海培训优势
 
  合作伙伴与授权机构



Altera全球合作培训机构



诺基亚Symbian公司授权培训中心


Atmel公司全球战略合作伙伴


微软全球嵌入式培训合作伙伴


英国ARM公司授权培训中心


ARM工具关键合作单位
  我们培训过的企业客户评价:
    曙海的andriod 系统与应用培训完全符合了我公司的要求,达到了我公司培训的目的。 特别值得一提的是授课讲师针对我们公司的开发的项目专门提供了一些很好程序的源代码, 基本满足了我们的项目要求。
——上海贝尔,李工
    曙海培训DSP2000的老师,上课思路清晰,口齿清楚,由浅入深,重点突出,培训效果是不错的,
达到了我们想要的效果,希望继续合作下去。
——中国电子科技集团技术部主任 马工
    曙海的FPGA 培训很好地填补了高校FPGA培训空白,不错。总之,有利于学生的发展, 有利于教师的发展,有利于课程的发展,有利于社会的发展。
——上海电子学院,冯老师
    曙海给我们公司提供的Dsp6000培训,符合我们项目的开发要求,解决了很多困惑我 们很久的问题,与曙海的合作非常愉快。
——公安部第三研究所,项目部负责人李先生
    MTK培训-我在网上找了很久,就是找不到。在曙海居然有MTK驱动的培训,老师经验 很丰富,知识面很广。下一个还想培训IPHONE苹果手机。跟他们合作很愉快,老师很有人情味,态度很和蔼。
——台湾双扬科技,研发处经理,杨先生
    曙海对我们公司的iPhone培训,实验项目很多,确实学到了东西。受益无穷 啊!特别是对于那种正在开发项目的,确实是物超所值。
——台湾欧泽科技,张工
    通过参加Symbian培训,再做Symbian相关的项目感觉更加得心应手了,理 论加实践的授课方式,很有针对性,非常的适合我们。学完之后,很轻松的就完成了我们的项目。
——IBM公司,沈经理
    有曙海这样的DSP开发培训单位,是教育行业的财富,听了他们的课,茅塞顿开。
——上海医疗器械高等学校,罗老师
  我们最新培训过的企业客户以及培训的主要内容:
 

一汽海马汽车 DSP培训
苏州金属研究院 DSP培训
南京南瑞集团技术 FPGA培训
西安爱生技术集团 FPGA培训,DSP培训
成都熊谷加世电气 DSP培训
福斯赛诺分析仪器(苏州) FPGA培训
南京国电工程 FPGA培训
北京环境特性研究所 达芬奇培训
中国科学院微系统与信息技术研究所 FPGA高级培训
重庆网视只能流技术开发 达芬奇培训
无锡力芯微电子股份 IC电磁兼容
河北科学院研究所 FPGA培训
上海微小卫星工程中心 DSP培训
广州航天航空 POWERPC培训
桂林航天工学院 DSP培训
江苏五维电子科技 达芬奇培训
无锡步进电机自动控制技术 DSP培训
江门市安利电源工程 DSP培训
长江力伟股份 CADENCE 培训
爱普生科技(无锡 ) 数字模拟电路
河南平高 电气 DSP培训
中国航天员科研训练中心 A/D仿真
常州易控汽车电子 WINDOWS驱动培训
南通大学 DSP培训
上海集成电路研发中心 达芬奇培训
北京瑞志合众科技 WINDOWS驱动培训
江苏金智科技股份 FPGA高级培训
中国重工第710研究所 FPGA高级培训
芜湖伯特利汽车安全系统 DSP培训
厦门中智能软件技术 Android培训
上海科慢车辆部件系统EMC培训
中国电子科技集团第五十研究所,软件无线电培训
苏州浩克系统科技 FPGA培训
上海申达自动防范系统 FPGA培训
四川长虹佳华信息 MTK培训
公安部第三研究所--FPGA初中高技术开发培训以及DSP达芬奇芯片视频、图像处理技术培训
上海电子信息职业技术学院--FPGA高级开发技术培训
上海点逸网络科技有限公司--3G手机ANDROID应用和系统开发技术培训
格科微电子有限公司--MTK应用(MMI)和驱动开发技术培训
南昌航空大学--fpga 高级开发技术培训
IBM 公司--3G手机ANDROID系统和应用技术开发培训
上海贝尔--3G手机ANDROID系统和应用技术开发培训
中国双飞--Vxworks 应用和BSP开发技术培训

 

上海水务建设工程有限公司--Alter/Xilinx FPGA应用开发技术培训
恩法半导体科技--Allegro Candence PCB 仿真和信号完整性技术培训
中国计量学院--3G手机ANDROID应用和系统开发技术培训
冠捷科技--FPGA芯片设计技术培训
芬尼克兹节能设备--FPGA高级技术开发培训
川奇光电--3G手机ANDROID系统和应用技术开发培训
东华大学--Dsp6000系统开发技术培训
上海理工大学--FPGA高级开发技术培训
同济大学--Dsp6000图像/视频处理技术培训
上海医疗器械高等专科学校--Dsp6000图像/视频处理技术培训
中航工业无线电电子研究所--Vxworks 应用和BSP开发技术培训
北京交通大学--Powerpc开发技术培训
浙江理工大学--Dsp6000图像/视频处理技术培训
台湾双阳科技股份有限公司--MTK应用(MMI)和驱动开发技术培训
滚石移动--MTK应用(MMI)和驱动开发技术培训
冠捷半导体--Linux系统开发技术培训
奥波--CortexM3+uC/OS开发技术培训
迅时通信--WinCE应用与驱动开发技术培训
海鹰医疗电子系统--DSP6000图像处理技术培训
博耀科技--Linux系统开发技术培训
华路时代信息技术--VxWorks BSP开发技术培训
台湾欧泽科技--iPhone开发技术培训
宝康电子--Allegro Candence PCB 仿真和信号完整性技术培训
上海天能电子有限公司--Allegro Candence PCB 仿真和信号完整性技术培训
上海亨通光电科技有限公司--andriod应用和系统移植技术培训
上海智搜文化传播有限公司--Symbian开发培训
先先信息科技有限公司--brew 手机开发技术培训
鼎捷集团--MTK应用(MMI)和驱动开发技术培训
傲然科技--MTK应用(MMI)和驱动开发技术培训
中软国际--Linux系统开发技术培训
龙旗控股集团--MTK应用(MMI)和驱动开发技术培训
研祥智能股份有限公司--MTK应用(MMI)和驱动开发技术培训
罗氏诊断--Linux应用开发技术培训
西东控制集团--DSP2000应用技术及DSP2000在光伏并网发电中的应用与开发
科大讯飞--MTK应用(MMI)和驱动开发技术培训
东北农业大学--IPHONE 苹果应用开发技术培训
中国电子科技集团--Dsp2000系统和应用开发技术培训
中国船舶重工集团--Dsp2000系统开发技术培训
晶方半导体--FPGA初中高技术培训
肯特智能仪器有限公司--FPGA初中高技术培训
哈尔滨大学--IPHONE 苹果应用开发技术培训
昆明电器科学研究所--Dsp2000系统开发技术
奇瑞汽车股份--单片机应用开发技术培训


 

 

 

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